With the widespread use of cellular phones, it has lately become essential to make effective use of radio wave resources, and attention is being focused on CDMA, and OFDM as wireless communication systems high in frequency utilization efficiency. It is known that momentary maximum power at about 10 dB or greater against average transmission power occurs to a transmitter at a base station for these systems.
Meanwhile, a power amplifier of the transmitter at the base station has a property such that high efficiency is generally obtained at the time of a large output operation, but there occurs deterioration in linearity at that time because of output saturation. Since such nonlinear distortion causes a transmitted spectrum to spread, resulting in interference with other bands, a quantity of disturbing waves generated is strictly regulated by Wireless Telegraphy Act.
With the transmitter at the base station, it is regarded preferable from the viewpoint of equipment size and running cost to execute operation in a high-efficiency state by raising output amplitude of the power amplifier, however, with CDMA, and OFDM, operation at high efficiency has become difficult to execute because nonlinear distortion is prone to occur thereto.
As a method of overcoming such a problem as described, various method of linearizing the output of the power amplifier by use of distortion-compensating techniques have so far been developed, and as one of such methods, digital predistortion for executing compensation for distortion in a baseband has been well known. The conventional configuration of the digital predistortion includes a configuration wherein a delay unit is made up of an FIR type digital filter (refer to Patent Document 1).
[Patent Document 1] JP-A No. 189685/2001
FIG. 3 shows a configuration example of a digital predistortion type transmitter at a wireless base station, and FIG. 4 shows a configuration of a predistortion unit 303 by way of example.
In FIG. 3, a transmission signal fed from a controller 300 is processed for coding by a modulator 301 to be subsequently subjected to bandwidth control by a baseband-signal-processing unit 302, which outputs quadrature IQ signals Ii, Qi to be further processed for compensation for distortion by a predistortion unit 303 to be thereby converted into analog signals by a D/A converter 304, and a quadrature modulator 305 executes conversion of frequencies of the analog signals into a radio frequency band, whereupon a power amplifier 306 amplifies power, thereby sending out radio waves into the air from an antenna 310 through an antenna sharing unit 309. In this case, nonlinear distortion occurs to the power amplifier 306 at the time of a large output, which, however, can be deemed equivalent to a case where the nonlinear distortion is superimposed on the output of a linear amplifier 307.
In order to effectively implement predistortion, it is necessary to accurately cancel out nonlinear characteristics of the power amplifier 306 by accurately grasping an amount of the nonlinear distortion that has occurred. Accordingly, transmission radio waves are converted in frequency to an IF band with the use of a mixer 311 to be subsequently converted into a digital signal by an A/D converter 312, and the digital signal is demodulated by a digital quadrature demodulator 313 to be thereby fed back to the predistortion unit 303. As for a configuration of a demodulation unit, a digital IF type excellent in demodulation precision has been described, however, various configurations other than that, including an analog quadrature modulator, are conceivable for adoption.
Next, referring to FIG. 4, a configuration of the predistortion unit 303 is described hereinafter. In FIG. 4, s delay unit 104 outputs signals Id, Qd obtained by delaying first input signals Ii, Qi by an integer (n) multiple of sample frequency. A subtractor 103 computes a difference between the signals Id, Qd, and second first input signals Ir, Qr. Based on a differential signal as obtained, an adaptive signal processor 102 controls a predistortor 101 so as to render the differential signal coming to zero. For adaptive signal processing, use is usually made of an algorithm for minimizing the square of an error, that is, distortion power, such as the least mean square algorithm, and recursive least square algorithm, based on the gradient method.
If nonlinear distortion has been accurately extracted by the subtractor 103, reduction in the nonlinear distortion can be implemented as a result of the adaptive signal processing described as above. However, if the extraction of the nonlinear distortion is incomplete, a control error results even in a state where the nonlinear distortion is at zero because the differential signal is not eliminated. In other words, in order to implement effective predistortion, it becomes necessary that delay on a signal path from the predistortor 101 to the quadrature demodulator 313 have been corrected by the delay unit 104.
However, while a delay quantity of the former does not always correspond to an integer multiple of the sample frequency since the same passes through analog elements, a delay quantity of the latter corresponds to nothing but the integer multiple of the sample frequency since the same is generated in a latch circuit. More specifically, if the delay quantity of the former is broken down into a component “n” corresponding to the integer multiple of the sample frequency, and a component “a” less than one sample frequency, the component “n” can be corrected, but it is difficult to correct the component “a.”
In Patent Document 1, there is disclosed a technology for correcting a delay quantity “a” less than one sample frequency. In this case, use is made of an FIR filter as means for causing the delay quantity less than one sample frequency to occur. In the case of this example, follow-up property thereof, against variation in delay time, is poor because delay time is decided prior to the start of a distortion-compensation operation. Accordingly, there is disclosed an example of creating a delay locked loop for controlling a clock phase of the A/D converter 312.
With delay correction means using the FIR filter as described in the conventional technology, an amplitude characteristic becomes flat only in the case where a tap factor is “0 0 . . . .. 010 . . . .. 0 0”, and when delay is set to less than one sample frequency, there arises a problem that the amplitude characteristic intrinsically has waviness occurring thereto, thereby impairing accuracy in distortion extraction by subtraction. Further, since delay correction is implemented by means of the FIR, there is a tendency that relatively large and redundant delay (corresponding to not less than 16 samples in the case of an embodiment of the conventional technology) is added. thereby creating a factor for interfering with higher speed in adaptive signal processing.
Still further, there is a problem with the delay locked loop as described in the conventional technology in that there is the needs for analog components such as a D/A converter for controlling the clock of the A/D converter 312, a smoothing filter, and a VCO in addition to those components shown in FIG. 3. Furthermore, in addition to an increase in the number of the analog components, there is a problem with the performance thereof in that jitter is prone to occur to clock due to the effect of quantization noises of the D/A converter, and thermal noises of the VCO, and further, the retention capability of control voltage is low due to the effect of an offset voltage, thereby causing the delay locked loop susceptible to be out of sync at the time of no signal.